In semiconductor devices such as DRAMs (Dynamic Random Access Memories), a precharge circuit configured to precharge a main input/output line to a predetermined voltage is employed.
Patent Literature 1 discloses a semiconductor memory in which a main input/output line (global data line) is precharged to a ½ core potential or a ½ power supply potential. The semiconductor memory disclosed in Patent Literature 1 includes two precharge units between global data lines in order to prevent a precharge potential on the main input/output line from increasing or decreasing from the ½ core potential or the ½ power supply potential when a burst write operation is repeated.